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U4256BM
Frequency Synthesizer for Radio Tuning
Description
The U4256BM is a single chip frequency synthesizer in BICMOS technology. Together with the AM/FM IC U4255BM, it performs a complete AM/FM car radio front end, which is recommended also for RDS (Radio Data System) applications. It is controlled by 3-wire bus and contains also Digital to Analog Converters (DACs) for automatic alignment of the AM/FM tuner.
Features
D D D D D D
Reference oscillator up to 15 MHz (tuned) Oscillator buffer output (for AM up/down conversion) Two programmable 16-bit dividers Fine-tuning steps: AM 1 kHz, FM 2 kHz
Fast response time due to integrated loop push-pull stage
D Four programmable switching outputs (open drain) D Three DACs for software controlled tuner alignment D Low power consumption D High S/N ratio D Integrated band gap
necessary
3-wire bus (enable, clock and data; 3 V and 5 V microcontrollers acceptable)
*
only one supply voltage
Block Diagram
SWO1 SWO2 SWO3 SWO4 7 Tuning 13 OSCIN 12 OSCOUT 15 8 9 10
Oscillator
R- divider
Switching outputs
DAC3 3-bit VRef DAC2
5
DAC3
MX2LO
OSC buffer
CLK DATA EN
17 16 18
4
DAC2
3W- bus interface
DAC1
3
DAC1
AM/FM
VRef 6 VS PDO 1
FMOSCIN
19
FM- preamp
N- divider
Phase detector Band-gap
Current sources
2 11 GND
96 11799
PD
20 GNDan V5
14
Figure 1. Block diagram
Ordering Information
Extended Type Number U4256BM-AFS U4256BM-AFSG3 Package SSO20 SSO20 Remarks Taped and reeled
Rev. A2, 03-Nov-98
1 (14)
Preliminary Information
U4256BM
Pin Description
PDO 1 20 19 18 17 16 GNDan FMOSCIN EN CLK DATA MX2LO V5
PD 2 DAC1 3
DAC2 4 DAC3 VS 5
U4256BM
6 15 14
SWO1 7 SWO2 8 SWO3 9 SWO4 10
96 11944
13 OSCIN 12 OSCOUT 11 GND
Figure 2. Pinning
Circuit Description
The U4256BM is a single chip PLL circuit, designed for AM/FM RDS (Radio Data System) applications. The special design allows to build automatic alignment tuner systems. Two programmable DACs (Digital to Analog Converter) support the computer controlled alignment. The U4256BM has a very fast response time of maximum 800 ms (at 2 mA, fref = 100 kHz, measured on MPX signal). It performs a high signal to noise ratio. Only one supply voltage is necessary, due to a integrated band gap. The U4256BM is controlled via 3-wire bus.
2 (14)
Preliminary Information
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4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin 1 2 3
Function Analog output Current output Output 1, digital to analog converter DAC2 Output 2, digital to analog converter DAC3 Output 3, digital to analog converter VS Supply voltage analog part SWO1 Switching output 1 SWO2 Switching output 2 SWO3 Switching output 3 SWO4 Switching output 4 GND Ground, digital part OSCOUT Oscillator output OSCIN Oscillator input V5 Capacitor band gap MX2LO Oscillator buffer output DATA Data input CLK Clock EN Enable FMOSCIN FM-oscillator input GNDan Ground, analog part
Symbol PDO PD DAC1
Functional Description
The U4256BM is especially designed for AM up/down converter systems, together with the tuner U4255BM. Due to the integrated DACs, an automatic tuner alignment is possible. All the functions of the U4256BM can be software controlled via a serial 3-wire bus, consisting of Enable, Clock and Data. The format and procedure for the data transfer from the microcontroller is shown in figures 3, 4 and table Data Transfer. All requested data have to be transferred via 16-bit or 24-bit commands. Due to the 8-bit structure, the serial output interface of a microcontroller can be used for the data transfer. The PLL functions can be controlled by 24-bit commands, while the alignment functions are controlled by 16-bit commands. The alignment function control normally is set once by switching on the tuner. Then the tuner automatically will be aligned. The data for alignment are stored in a separate EPROM. Via integrated capacitors it is possible to tune the reference oscillator (this function is controlled via the 3-wire bus).
Rev. A2, 03-Nov-98
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Test conditions (unless otherwise specified): VS = +8.5 V, Tamb = +25C
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Electrical Characteristics
All voltages are referred to GND (Pin 15)
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Thermal Resistance
All voltages are referred to GND (Pin 15)
Rev. A2, 03-Nov-98 PD Output current 1 Output current 2 Output current 3 Output current 4 Leakage current Junction ambient
Operating Range
Absolute Maximum Ratings
Parameters Supply voltage Analog supply voltage Supply current Analog supply current OSCIN Input voltage FMOSCIN Input voltage
Supply voltage range Ambient temperature Input frequency Programmable divider Crystal oscillator
Analog supply voltage Input voltage Output current Output drain voltage Ambient temperature range Storage temperature range Junction temperature Electrostatic handling
Parameters when soldered to PCB
Parameters
Parameter
Pin 6 Pins 16, 17 and 18 Pins 7, 8, 9 and 10 Pins 7, 8, 9 and 10
Pins 12 and 13
Pin 6
Pin 19
Preliminary Information
Pin 13 f = 0.1 to 15 MHz Pin 19 f = 70 to 120 MHz f = 120 to 160 MHz Pin 2 PD = 2.5 V PD = 2.5 V PD = 2.5 V PD = 2.5 V PD = 2.5 V Test Conditions / Pins Pin 6 Pin 20 Symbol VS Tamb RFi SF fXTAL Symbol RthJA Symbol VS VI IO VOD Tamb Tstg Tj VESD VFMOSC VFMOSC Symbol IPDL IPD VOSC VA IA Min. 8 -40 70 2 0.1 20 80 400 1600 Min. 40 150 100 4.5 8 Value 8 to 15 -0.3 to +12 -1 to +5 15 -40 to +85 -40 to +125 125 t.b.d. Value 140 Typ. 8.5 25 100 500 2000 Typ.
U4256BM
8.5
10
Max. 14 +85 160 65535 15
Max.
30 120 600 2400 20
20
12
Unit K/W
Unit V V mA V C C C V
mVrms mVrms
mVrms
MHz
Unit V C MHz
Unit
mA
3 (14) A A A A nA V
A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A AAA A A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAA A A AAA A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Test conditions (unless otherwise specified): VS = +8.5 V, Tamb = +25C
3-Wire Bus Description
Electrical Characteristics (continued)
U4256BM
4 (14)
EN
Parameters Test Conditions / Pins Symbol PDO Pin 1 Saturation voltage HIGH VSATH - (VA - VPDOFM), VSATH LOW I = 15 mA VSATL SWO1, SWO2, SWO3, SWO4 (open drain) Pins 7, 8, 9 and 10 I = 1 mA, Output leakage current IOHL V7,8,9,10 = 8.5 V HIGH Output voltage LOW VSWOL DAC1, DAC2 Pins 3 and 4 Output current IDAC1, 2 Output voltage VDAC1, 2 Gain range (resolution 256 steps) Offset range (resolution 24 steps) DAC 3 Pin 5 Output current IDAC3 Output voltage (resolution 16 steps) VDAC3 MX2LO Output AC voltage At Pin15: 47 pF and 1 kW VMX2LO Output DC voltage VDC
DATA
e.g., Divider
24-bit command
16-bit command
CLK
CLK
DATA
EN
LSB
LSB
20
21
22
BYTE 1
BYTE 1
23
24
25
R-Divider
26
MSB LSB
MSB LSB
Preliminary Information
27 28 29
Figure 3. Pulse diagram
2 10
2 11
BYTE 2
BYTE 2
2 12
2 13 2 14
MSB
MSB LSB
2 15 P-20 P-21 P-22
Status 0
Min.
0.25
0.3 0.6 -0.6
100
80 1.6
OSCB IPD4 IPD2
BYTE 3
IPD3 IPD1
Typ.
120 1.9
100
200
Rev. A2, 03-Nov-98 1 VS - 0.5 2.3 0.7
0 Addr.
Max.
200 2.1
400
100
500 400
1 6
MSB
0
14858
mVpp V Unit mA V mA V mV mV mV nA V
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E D C B A
Rev. A2, 03-Nov-98
Data Transfer
MSB ADDR. 1 0 8pF B85
0 1 O-25 B13
01
0 0 O-25 B49
0 0 IPD 1,2
MSB ADDR.
MSB ADDR.
MSB ADDR.
MSB ADDR.
B35
B71
0
B70
IPD 3,4
AM = 1 FM = 0
BYTE 2 LSB MSB Oscillator tuning function 32pF 16pF 8pF 4pF 2pF 1pF 0.5pF B84 B83 B82 B81 B80 B79 B78
O-24 B12
O-24 B48
B34
BYTE 2 LSB MSB DAC2 - GAIN & OFFSET
BYTE 2 LSB MSB DAC1 - GAIN & OFFSET
Byte 3 STATUS 1
Byte 3 STATUS 0
OSCB 0 = on, 1 = off
O-23 B11
O-23 B47
B69
SWO4 1=off, 0=on
B33
O-22 B10
O-22 B46
P-22
B68
SWO3 1=off, 0=on
B32
O-21 B9
O-21 B45
P-21
B67
SWO2 1=off, 0=on
O-20 B8
O-20 B44
B31
LSB
LSB
P-20
B66
Preliminary Information
G-27 B7 G-27 B43 SWO1 1=off, 0=on
MSB
B30
B65
215
G-26 B6
G-26 B42
MSB
B64
214
B29
215
G-25 B5
G-25 B41
B63
213
B77
B28
214
BYTE 2
BYTE 1
BYTE 1
G-24 B4
G-24 B40
BYTE 1
B62
212
B76
B27
213
BYTE 2
G-23 B3
G-23 B39
B61
211
B25
212
B75
B60
210
G-22 B2
G-22 B38
B24
211
B74
LSB N - DIVIDER
LSB MSB R - DIVIDER
B59
29
G-21 B1
G-21 B37
B23
210
LSB
LSB
B73
LSB
B58
28
B22
G-20 B0
G-20 B36
29
B72
B57
27
B22
28
B56
26
MSB
B21
27
B55
25
U4256BM
B20
26
BYTE 1
B54
24
B19
25
B53
23
B18
BYTE 1
24
B52
22
B17
23
B51
21
B16
5 (14)
22
LSB
B50
20
B15 21
LSB
B14 20
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Timing Information
Bus Timing
U4256BM
6 (14) Parameters Test Conditions / Pins 3-wire bus, ENABLE, DATA, CLOCK Pins 16, 17, 18 Input voltage HIGH LOW Clock frequency Period of CLK HIGH LOW Rise time EN, DA, CLK Fall time EN, DA, CLK Set-up time Hold time EN Hold time DA Enable Clock Data tR tS tR tS tR tH tL tHDA
Figure 4. Bus timing
Preliminary Information
Symbol VBUS VBUS tHEN tHDA tH tL tr tf ts Min. 100 250 0 250 250 2.0 tF tF Typ. tHEN
96 11826
Rev. A2, 03-Nov-98 Max. tF 400 100 1.0 1.0 V V MHz ns ns ns ns ns ns ns Unit
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The switching output SWO1 to SWO4 can be controlled as following (Bits 30 to 33): Switch Output Bit SWOx = ON 0 SWOx = OFF 1 The FM/AM function can be controlled by setting the FM/AM Bit 34 as following: FM/AM Bit 34 FM 0 AM 1 The tuning capacity for the crystal oscillator has a range of 0.5 pF to 71.5 pF. The values are coded binary. The tuning can be controlled by the Bits 78 to 85 as following:
C (pF) 0 0.5 1.0 1.5 ... 63.5 71.5 B85 1 1 1 1 ... 1 0 B84 1 1 1 1 ... 0 0 0 0 0 0 ... 0 ... 1 1 1 B83 1 1 1 1 ... 0 0 0 0 0 0 ... 1 ... 1 1 1 B82 1 1 1 1 1 1 1AAA1 1 1 1 1 ... ... ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...AAA ... 1 1 ... ... 1 1 1 1 1 1 B81 B80 0 0 1 1 ... 1 ... 0 1 1 B79 1 1 0 0 ... 0 0 B78 0 1 0 1 ... 0 ... 1 0 1 1 0 1 0 ... 0 0
AAAAAAAAAAAAAAAA A AAA A A AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAA A A AA A A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA A A A AA A AAA A A AA A AAAAAAAAAAAAAAAA A A A AA A A A A AA A AAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAA AAAAAAAAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A AA A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAA A A A A AA A AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAA AA AA AA AA AAAA AA AA AA A AAAAAAAAAAAAAAAA AA AA AA AA A AAAA AA AA AA AAAAAAAAAAAAAAAA AA AA AA AA AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA AAAA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA AAAAAAAAAAAAAAAA AA AA AA AA AAAAAAAAAAAAAAAA AA AA AA AA AAAA AA AA AA AAAAAAAAAAAAAAAA AA AA AA AA AA AA AA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A AA AA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A AA AA AA A AAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA A AA AA AA AAAAAAAAAAAAAAAA AA AAAAAAA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAAAAAA A
The DAC3 output voltage can be controlled by the Bits P-20 to P-22 (Bits 66 to 68) as following: DAC3 Offset Approx. Bit68 Bit67 Bit66 0.5 V 0 0 0 1.1 V 0 0 1 1.8 V 0 1 0 2.4 V 0 1 1 3.1 V 1 0 0 3.7 V 1 0 1 4.4 V 1 1 0 5.0 V 1 1 1 The oscillator buffer output can be switched by the OSCB Bit as following (Bit 69): MX2LO AC Voltage OSCB ON 0 OFF 1 The charge pump current can be choosen by setting the Bits IPD1, 2 (Bit 71) and IPD3, 4 (Bit 70) as following: IPD (A) IPD1, 2 IPD3, 4 25 0 0 100 0 1 500 1 0 2000 1 1
Rev. A2, 03-Nov-98
Bus Control
Preliminary Information
The offset of DAC1 has a range of 0.5 to -0.6. This range is divided into 64 steps. So one step is approximately 1.1V/63 = 17.2 m. The offset can be controlled by the Bits 44 to 49 (O-20 to O-25) as following: The gain of DAC1 has a range of 0.7 x V(PDO) to 2.15 x V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (2.15-0.7)/256 = 5.664 m. The gain can be controlled by the Bits 36 to 43 (G-20 to G-27) as following:
Offset DAC1 Approx. 0.5 0.4828 0.4656 0.4484 ... -0.0156 ... 0.5656 -0.5828 -0.6 Gain DAC1 Approx. 0.7 0.70566 0.71133 0.71699 ... 1.00019 ... 2.1386 2.14434 2.15 m B43 B42 B41 B40 B39 B38 B37 B36 0 0 0 0 ... 0 ... 1 1 1 B49 0 0 0 0 ... 0 ... 1 1 1 B48 0 0 0 0 ... 1 ... 1 1 1
U4256BM
B47
0 0 0 0 ... 1 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
B46
0 0 0 0 ... 1 ... 1 1 1
B45
0 0 1 1 ... 0 ... 0 1 1
7 (14)
B44 0 1 0 1 ... 1 ... 1 0 1
U4256BM
The gain of DAC2 has a range of 0.7 x V(PDO) to 2.15 x V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (2.15-0.7)/256 = 5.664 m. The gain can be controlled by the bits 0 to 7 (G-20 to G-27) as following:
Gain DAC2 Approx. 0.7 0.70566 0.71133 0.71699 ... 1.00019 ... 2.1386 2.14434 2.15 m B7 B6 B5 B4 B3 B2 B1 B0
The offset of DAC2 has a range of 0.5 to -0.6. This range is divided into 64 steps. So one step is approximately 1.1V/63 = 17.2 m. The offset can be controlled by the Bits 8 to 13 (O-20 to O-25) as following:
Offset DAC2 Approx. 0.5 0.4828 0.4656 0.4484 ... -0.0156 ... 0.5656 -0.5828 -0.6 B13 0 0 0 0 ... 0 ... 1 1 1 B12 0 0 0 0 ... 1 ... 1 1 1 B11 0 0 0 0 ... 1 ... 1 1 1 B10 0 0 0 0 ... 1 ... 1 1 1 B9 0 0 1 1 ... 1 ... 0 1 1 B8 0 1 0 1 ... 0 ... 1 0 1
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0 0 0 0 ... 0 ... 1 1 1 0 0 0 0 ... 0 ... 1 1 1 0 0 0 0 ... 1 ... 1 1 1 0 0 0 0 ... 1 ... 1 1 1 0 0 0 0 ... 0 ... 1 1 1 0 0 0 0 ... 1 ... 1 1 1 0 0 1 1 ... 0 ... 0 1 1 0 1 0 1 ... 1 ... 1 0 1
Input / Output Interface Circuits
PDO
PDO is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier.
PD
PD is the current charge pump output of the PLL. The current can be controlled by setting the Bits IDP1, 2 and IDP3, 4. The loop filter has to be designed corresponding to the choosen pump current and the internal reference frequency. A recommendation can be found in the application circuit.
14859
V5 V5
C PDO
PD
Figure 5.
8 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
FMOSCIN
FMOSCIN is the preamplifier input for the FM/AM oscillator signal.
FMOSCIN AMOSCIN
14860
Figure 6.
MX2LO
MX2LO is the buffered output of the crystal oscillator. V5 V5
EN, DATA, CLK
All functions can be controlled via a 3-wire bus consisting of ENABLE, DATA and CLOCK. The bus is designed for microcontrollers which operate with 3 V supply voltage. Details of the data transfer protocol are shown in the table `Data Transfer'.
VDD
OSCIN MX2LO
EN DATA CLK
14863
14861
Figure 7.
Figure 9.
DAC 1, 2 and 3
DAC 1 to 3 are the outputs for automatic tuner alignment. VS
SWO1, 2, 3 and 4
All switching outputs are `open drain' and can be set and reset by software control. Details are described in the data transfer protocol.
SWO1 SWO2 SWO3 SWO4
DAC1
14862
14864
Figure 8.
Figure 10.
Rev. A2, 03-Nov-98
9 (14)
Preliminary Information
U4256BM
OSCIN, OSCOUT
A crystal resonator (up to 16 Mhz) is connected between OSCIN and OSCOUT in order to generate the reference frequency. The complete application circuit is shown in figure 15. If a reference is available, it can be applied at OSCIN. The minimum voltage should be 100mVrms. In this case, pin OSCOUT has to be open.
VDD
OSCIN
VDD
OSCOUT
14865
Figure 11.
Application Information
Function of DAC1, 2 in the FM Mode
For automatic tuner alignment, the DAC1 and 2 of the U4256BM can be controlled by setting gain and offset values. The following figure shows the principle of the operation in FM mode. The gain is in the range of 0.7 to 2.15. The offset range is +0.5 V to -0.6 V. For alignment, DAC1 and 2 are connected to the varicaps of the preselection filter and the IF filter. For alignment, offset and gain is set for having the best tuner tracking
Function of DAC1, 2 in the AM Mode
In AM mode, DAC1, 2 can be used as standard DAC converters. The resolution of 8 bit is controlled via the gain bits in a range of approximately 0.5 V to 7 V, depending on the offset value.
FMOSCIN Sensitivity
Vi (mVrms on 50 W) 150
PDO
Gain
+/-
DAC1,2
100
50
Offset
14907
0 0 20 40 60 80 100 120 Frequency (MHz) 140 160
Figure 12.
Figure 13.
10 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
Oscillator Tuning Function Schematic
Cx1 Cx2
INV
8p 32p 16p 8p 4p 2p 1p .5p
.5p
1p
2p
4p
8p
16p
32p
8p
B78
B79 B80 B81 B82 B83 B84 B85
Figure 14.
Application Circuit
EN CLK DATA V5 C 12 100 nF GND
R5 C8 47 pF 20 C1 10 pF R2 600 19 18 17 16 15 14
C9 33 pF
5.1 k 33 pF 4 MHz 13 12
11
U4256BM
1 2 C7 10 nF C 14 10 nF C 15 10 nF 10 nF C4 100 F R3 100 DAC2 DAC3 VS SWO1 SWO2 SWO3 SWO4 8 ... 12 V 100 nF 3 4 C16 5 6 C5 7 8 9 10
FM OSC
C6 330 pF
R4 10 k
DAC1
9611257
Figure 15. Application circuit
Rev. A2, 03-Nov-98
11 (14)
Preliminary Information
R 106 MP1 UG10V MP2 DPLPF 100nF R 201 C 202 MP9 C 208 220nF R 303 2.2k W F302 AM/ZF2 6 10nF 7 C 204 C 207 220nF C 310 R 111 200k W 1.5nF R 152 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 10 W C 40 220 nF 1 3 10nF C 312 KF302 450kHz 470nF C 113 C 112 10 m F R8 1kW R 104 470 W R 105 10W 1 R 10 C 114 C 303 C 304 220nF 47pF F131 3 1nF C 110 4.7n F D 131 10nF BB804 R 121 68k W R 131 5.6kW 7 C 156 10nF C 155 100nF 10.25 MHz C 134 20 19 18 17 16 15 14 13 12 11 C 153 22pF Q151 C 154 22pF F102 3 D 102 68kW BB804 C 107 18pF 2 R 102 6.8pF FM0 1 22pF C 133 6.8pF MP12 EN 22n F 10 m F C 108 C 109 C 131 C 132 C 44 R 11 2.2kW 390W 220 nF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MP4 IF2 MP5 STOP MP10 DATA MP11 CLOCK 100 nF 10 m F 10nF C 205 C 206 2 4 100nF KR202 10.7 MHz 10nF 6 2 C 209 3 1 C 309 C 307 220nF AM/ZF1 F201 C 313 10nF L7 68 m H C 306 15pF 270pF 68 m H L8 100nF KR201 10.7MHz 10kW C 201 R 202 4 1nF C 203 270 W C 313 HUB MP3 C 308 10 W
U4256BM
Application Board Schematic
12 (14)
7
L9
2.2 m H
R 12
2.7kW
U4255BM
T301 BC848C
T302 BC858C
MPF102 J109
R 16
47 W
470k W
C 53 1 R 112 C 104 C 106 10nF 10pF F101 7 4 100nF 1 3 R 151 8.2kW R 122 C 103 68kW D 101 BB804 C 102 D 103 S391D 10nF R 103 680 W L 301 5mH C 301 10pF D 301 S391D C 115 D 302 S391D 100nF C 116 100nF FMV C 311 6 T101 BFR93A T301 BC858C 47kW
C 54
Figure 16. Application borad schematic
220 nF
1nF
Preliminary Information
L 102 2.2 m H R 113 10kW 1nF
C 117
10nF
U4256BM
1 2 3 4 5 6 7 8 9 10
C 152 330pF
C 151 10nF C 157 10nF 100
mF
MP6 MPX MP7 ADJ MP8 FELD
3.9pF
Rev. A2, 03-Nov-98
14522
U4256BM
Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications 13007
1
10
Rev. A2, 03-Nov-98
13 (14)
Preliminary Information
U4256BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
14 (14)
Rev. A2, 03-Nov-98
Preliminary Information

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